myownla.blogg.se - Download free jfet

where V gs is made sufficiently negative, I d is reduced to zero. As we know that if V gs is more negative curves drain current to reduce.Plot the graph between gate to source voltage along the horizontal axis and current I d on the vertical axis.First adjust the drain to source voltage to some suitable value, then increase the gate to source voltage in small suitable value.These curves show the relationship between drain current I d and gate to source voltage V gs for different values of V ds. It is important to note that the maximum voltage V ds which can be applied to FET is the lowest voltage which causes available breakdown.The maximum saturation drain current is smaller.

The avalanche break down occurs at progressively lower value of V ds because the reverse bias gate voltage adds to the drain voltage thereby increasing effective voltage across the gate junction.

It is because of the gate to source junction due to avalanche effect.

In this region, the drain current increases rapidly as the drain to source voltage is increased.

The drain current in the pinch off region depends upon the gate to source voltage and is given by the relation.

In this drain current remains constant at its maximum value I dss.

To use FET as an amplifier it is operated in this saturation region. Because of the channel is occupied with depletion region, the depletion region is more towards the drain and less towards the source, so the channel is limited, with this only limited number of carriers are only allowed to cross this channel from source drain causing a current that is constant in this region.

It is also called as saturation region or constant current region.

This is the region shown by the curve as saturation region.

The drain to source voltage at which channel pinch off occurs is called pinch off voltage(V p). All the drain to source voltage corresponding to point the channel width is reduced to a minimum value and is known as pinch off.Ħ. As a result of this depletion region grows in size thereby reducing the effective width of the channel.ĥ. This in turn increases the reverse bias voltage across the gate source junction. It is because of the fact that there is an increase in V ds.

Here the drain current is increased slowly as compared to ohmic region.Ĥ. I d increases with increase in drain to source voltage. This shows that FET behaves like an ordinary resistor. When V ds is applied and it is increasing the drain current I d also increases linearly up to knee point.Ģ. In order to explain typical drain characteristics let us consider the curve with V gs= 0 V.ġ. There are two important characteristics of a JFET.ĭrain characteristics show the relation between the drain to source voltage V ds and drain current I d. The family of curves that shows the relation between current and voltage are known as characteristic curves.